Were they marvels, though? Itanium made good business sense in that it would cut AMD out of the market, but it was shit technology. Itanium would have also done a good job of cutting GCC out of the compiler market, which is great news for ICC. If everybody had to buy Intel compilers, boy that would have changed the software market.
You shouldn’t be making the compiler guess at conditions-on-the-ground that the CPU should be inferring itself, such as “which data dependencies are in cache and could be running OOO right now?”. You shouldn’t be making the compiler spend instructions and memory bandwidth describing this stuff. You shouldn’t be making code that works well on exactly one generation of CPU, one pipeline design, and is trash on the next generation. Once upon a time, MIPS saved a few gates by making three “delay slots” part of the ISA, and that became an albatross as soon as they weren’t a three stage pipeline. Itanium is all about making that kind of design decision everywhere. Itanium is the Microsoft Word of ISAs, where the spec is “whatever my implementation does is the correct thing”
The immediate failure of the Itanium was the promise that “you are buying a new, more expensive system that runs your current x86 code worse”, and the expectation was that every generation of Itanium would go like that. Just as your software starts getting good, here comes the new chip that will someday make stuff faster, but you will never see that until just about the end of that product cycle.
Were they marvels, though? Itanium made good business sense in that it would cut AMD out of the market, but it was shit technology. Itanium would have also done a good job of cutting GCC out of the compiler market, which is great news for ICC. If everybody had to buy Intel compilers, boy that would have changed the software market.
You shouldn’t be making the compiler guess at conditions-on-the-ground that the CPU should be inferring itself, such as “which data dependencies are in cache and could be running OOO right now?”. You shouldn’t be making the compiler spend instructions and memory bandwidth describing this stuff. You shouldn’t be making code that works well on exactly one generation of CPU, one pipeline design, and is trash on the next generation. Once upon a time, MIPS saved a few gates by making three “delay slots” part of the ISA, and that became an albatross as soon as they weren’t a three stage pipeline. Itanium is all about making that kind of design decision everywhere. Itanium is the Microsoft Word of ISAs, where the spec is “whatever my implementation does is the correct thing”
The immediate failure of the Itanium was the promise that “you are buying a new, more expensive system that runs your current x86 code worse”, and the expectation was that every generation of Itanium would go like that. Just as your software starts getting good, here comes the new chip that will someday make stuff faster, but you will never see that until just about the end of that product cycle.
Honestly, that fits my experience working at an itanium customer.